In high-speed integrated circuit (IC) processors or communications systems, phase-locked loops (PLL) are often used to obtain clock signals with accurate frequencies and phases. For example, in a radio frequency (RF) transmitter, a PLL may be used to synthesize a carrier frequency based on a reference frequency; and in an RF receiver, a PLL may be used to recover the carrier frequency from the received signals. For another example, in a system composed of multiple IC chips, PLL's may be used in the chips for synchronization with one another, or to provide internal clock signals having precise timing relationships but higher frequencies than external signals.
Examples of conventional PLL's include linear PLL's, digital PLL's, and all-digital PLL's. These three types are illustrated in FIGS. 1-3, respectively, and briefly described below.
FIG. 1 shows the structure of a linear PLL, also known as an analog PLL or APLL. The linear PLL includes a phase detector 102, a loop filter 104, and a voltage controlled oscillator (VCO) 106. Phase detector 102 mixes an output signal of VCO 106 with a reference signal to generate a mixture signal containing a sum frequency component, i.e., a component reflecting the sum of the frequency of the output signal and the frequency of the reference signal, a difference frequency component, i.e., a component reflecting the difference between the frequency of the output signal and the frequency of the reference signal, and a phase difference component, i.e., a component reflecting the difference between the phase of the output signal and the phase of the reference signal. Loop filter 104 filters out the sum frequency component from the mixture signal, and outputs the difference frequency component and the phase difference component to VCO 106. VCO 106 outputs the output signal having an oscillation frequency determined by the frequency difference and the phase difference. The linear PLL is configured as a negative feedback loop such that when the frequency of the output signal is lower than that of the reference signal, the output of loop filter 104 controls VCO 106 to raise the frequency of the output signal. Conversely, when the frequency of the output signal is higher than that of the reference signal, the output of loop filter 104 controls VCO 106 to lower the frequency of the output signal. As a result, when the linear PLL is stabilized, the output signal of VCO 106 should have the same frequency and phase as the reference signal; in other words, the output signal of VCO 106 is locked to the reference signal.
FIG. 2 shows the structure of a digital PLL, often abbreviated as DPLL. The DPLL includes a phase and frequency detector (PFD) 202, a charge pump 204, a loop filter 206, a VCO 208 for generating an oscillation signal, and a frequency divider 210 for generating a divided frequency signal having a frequency that is 1/N of the frequency of the oscillation signal, where N is an integer. PFD 202 compares a divided frequency signal with a reference signal and provides a control signal to charge pump 204 indicating whether the frequency of the oscillation signal should increase or decrease. Charge pump 204 includes a charge storage component and outputs a voltage in proportion to the amount of charge stored in the charge storage component. Loop filter 206 filters out high frequency components in the output of charge pump 204. The frequency of the oscillation signal generated by VCO 208 is determined by the output voltage of charge pump 204 as filtered by loop filter 206. Frequency divider 210 receives the oscillation signal and generates the divided frequency signal. The DPLL is configured such that the oscillation signal has a frequency N times that of the reference signal. Thus, when the frequency of the oscillation signal is higher than N times the frequency of the reference signal, charge pump 204 operates to lower the frequency of the oscillation signal generated by VCO 208. Conversely, when the frequency of the oscillation signal is lower than N times the frequency of the reference signal, charge pump 204 operates to raise the frequency of the oscillation signal generated by VCO 208. Thus, when the DPLL is in a locked state, the frequency of the oscillation signal generated by VCO 208 should be N times the frequency of the reference signal. Frequency divider 210 may also be configured to output M/N of the frequency of the oscillation signal, where M, N are integers. Therefore, the DPLL has great flexibility to generate an oscillation signal having almost any frequency.
The APLL and DPLL respectively shown in FIGS. 1 and 2 both use a VCO. The VCO is an analog circuit, which occupies a large chip area and has poor noise immunity. In contrast, an all-digital PLL, or ADPLL, utilizes a digitally controlled oscillator (DCO) instead of a VCO. FIG. 3 shows the structure of an ADPLL. The ADPLL includes a PFD 302, a control unit 304, a DCO 306, and a frequency divider 308. PFD 302 compares an output signal of frequency divider 308 with a reference signal and provides a signal to control unit 304 indicating whether the frequency of the output signal should increase or decrease. Control unit 304 generates control signals based on the output of PFD 302 for controlling DCO 306 to adjust the frequency of an oscillation signal generated by DCO 306. Frequency divider 308 receives the oscillation signal and generates a signal having a frequency equal to 1/N of the frequency of the oscillation signal. When the ADPLL is in a locked state, the frequency of the oscillation signal generated by DCO 306 should be N times the frequency of the reference signal.
The ADPLL includes only digital components and only processes digital signals. Therefore, the ADPLL has better noise immunity than the APLL or DPLL. Moreover, in the APLL and DPLL, the frequency of the oscillation signal is adjusted solely based on the feedback of the oscillation signal to the phase detector or phase and frequency detector. In contrast, the ADPLL uses control unit 304 to control DCO 306 for adjusting the frequency of the oscillation signal. Once PDF 302 determines the frequency difference and phase difference, control unit 304 calculates the amount of frequency adjustment required for the oscillation signal. As a result, the ADPLL may reach a locked state more quickly than the APLL or DPLL.
A DCO generally includes a number of inverters forming a loop. FIG. 4A shows a configuration of a conventional DCO 400 including eight inverters 402, i.e., 402-1, 402-2, . . . , and a NAND gate 404. The eight inverters 402 and NAND gate 404 form a loop, such that the output of one of inverters 402 or NAND gate 404 is the input of a next one of inverters 402 or NAND gate 404 on the loop, as FIG. 4A shows. NAND gate 404 also receives an enable signal that enables DCO 400. When the enable signal is “1”, NAND gate 404 becomes an inverter, too, and the loop of DCO 400 becomes a positive feedback loop containing nine inverters. As a result, DCO 400 starts to oscillate. FIG. 4A shows that the output of inverter 402-4 is provided as the output of DCO 400. However, it is apparent that the output signal may be taken out at any point of the loop. DCO 400 shown in FIG. 4A is generally referred to as a double-edge-triggered DCO, because either a fall or a rise in a signal at any point of the loop would trigger a change in the output signal.
Because the period of the output oscillation signal is the total circuit delay of the loop, by changing the total circuit delay of the loop, the period and frequency of the oscillation signal can be adjusted. FIG. 4A shows that control signals are provided to each of inverters 402 for controlling the circuit delay thereof, and FIG. 4B illustrates one exemplary configuration of one of inverters 402 with a circuit delay controllable by external control signals. The configuration of FIG. 4B was disclosed by J. Dunning et al., An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors, IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412-22, Apr. 1995. As FIG. 4B shows, inverter 402 includes a standard CMOS inverter 406 composed of a PMOS transistor 408 and an NMOS transistor 410. A number of PMOS transistors 412 connected in parallel are provided as the load on the side of PMOS transistor 408, and a number of NMOS transistors 414 connected in parallel are provided as the load on the side of NMOS transistor 410. The control signals are separately provided to the respective gates of PMOS transistors 412 and NMOS transistors 414 to select one or more of PMOS transistors 412 and the corresponding one or more of NMOS transistors 414.
PMOS transistors 412 and NMOS transistors 414 are provided in pairs and each pair has different dimensions than others. For example, gate widths of the pairs of PMOS transistors 412 and NMOS transistors 414 may increase by a factor of 2 from the smallest size to 256 times the smallest size, as indicated by the numbers 256, 128, . . . , in FIG. 4B. As a result, each one of PMOS transistors 412 has different capacitances in the on and off states thereof than the others, and each one of NMOS transistors 414 has different capacitances in the on and off states thereof than the others. Consequently, providing different control signals to select one or more different pairs of PMOS transistors 412 and NMOS transistors 414 results in a different circuit delay of inverter 402, and therefore, a different oscillation frequency of DCO 400.
The control signals for selecting PMOS transistors 412 and NMOS transistors 414 are generally binarily weighted, and may be collectively referred to as a control word. For example, assuming N=8, then there are 8 pairs of PMOS transistors 412 and NMOS transistors 414, which can produce 28 different oscillation frequencies. A control word of 00000000 turns off all of PMOS transistors 412 and NMOS transistors 414, producing the maximum delay and therefore the lowest possible oscillation frequency; a control word of 11111111 turns on all of PMOS transistors 412 and NMOS transistors 414, producing the minimum delay and therefore the highest possible oscillation frequency; and any intermediate control word would select a combination of PMOS transistors 412 and NMOS transistors 414 that produce a corresponding intermediate oscillation frequency. Increasing the binary code by 1 results in a minimal increase in the oscillation frequency, which is defined as the resolution of the DCO. Apparently, the resolution of the DCO is determined by the smallest possible capacitance adjustment in the load of the inverters, e.g., the capacitance change in the smallest one of PMOS transistors 412 and NMOS transistors 414 between the on and off states.
Because transistors have different capacitances when they are turned on and off, DCO 400 shown in FIGS. 4A and 4B realizes different delays by adjusting a capacitive load of inverters 402 through selectively turning on and off transistors. In this sense, PMOS transistors 412 and NMOS transistors 414 may be referred to as variable capacitors (varactors) and, particularly, digitally controlled varactors (DCV's), because they are controlled by digital signals. In addition to transistors configured to provide different capacitances in their on and off states as shown in FIG. 4B, transistors may be configured in other manners as varactors to be used in DCO's. For example, FIG. 5A shows an inverter having a conventional DCV as the load thereof. In FIG. 5A, the DCV comprises a NOR gate coupled to receive the output of the inverter and a control signal D. The NOR gate comprises four transistors, including two NMOS transistors M1 and M2 and two PMOS transistors M3 and M4. The source of PMOS transistor M3 and the drain of PMOS transistor M4 are connected together but not connected to any bias voltage. Depending on the control signal D, the NOR gate exhibits different capacitances. For example, when D is 1, NMOS transistor M2 is on, the drain of PMOS transistor M3 is grounded, and the source of PMOS transistor M3 is floating; and when D is 0, PMOS transistor M4 is turned on, the source of PMOS transistor M3 is biased at the voltage of the positive power supply, and the drain of PMOS transistor M3 is either grounded (when the output of the inverter is 1) or at the potential of the positive power supply (when the output of the inverter is 0). As a result of these different bias voltages on the source and drain of PMOS transistor M3, the NOR gate exhibits different capacitances. Therefore, the delay of the circuit shown in FIG. 5A varies with the control signal D. FIG. 5B is a graph illustrating the change of the gate capacitance of PMOS transistor M3 with a voltage applied at the gate of PMOS transistor M3 under the two possibilities of the control signal D. The abscissa shows the voltage of the output, Vout, and the ordinate shows the capacitance of PMOS transistors M3 and the combined capacitance of PMOS transistors M1 and M3. The bolded line shows the capacitances when the control signal D is 1, and the non-bolded line shows the capacitances when the control signal D is 0. As FIG. 5B shows, the capacitance of M3 and the combined capacitance of M1 and M3 both when the control signal D changes. The frequency of a DCO using the inverter of FIG. 5A is determined by the delay of the inverter, which is in turn determined by the capacitance of the DCV averaged over the range of the output of the inverter, which is also the gate voltage of PMOS transistor M3. Therefore, the resolution of such a DCO is determined by the change in the average capacitance of the DCV when the control signal D changes between 1 and 0, which is smaller than a change in a gate capacitance of a transistor configured to operate in only on and off states, such as PMOS transistors 412 and NMOS transistors 414 shown in FIG. 4B. Consequently, the resolution of a DCO composed of inverters such as that shown in FIG. 5A is higher than DCO 400 as shown in FIGS. 4A and 4B.
FIG. 6A shows another conventional DCV 600 including an NMOS transistor 602 and a PMOS transistor 604. The source and drain of NMOS transistor 602 are connected together and coupled to receive a control signal D. The source and drain of PMOS transistor 604 are connected together and coupled to receive the invert, DB, of control signal D. The substrate of NMOS transistor 602 is grounded and the substrate of PMOS transistor 604 is coupled to a positive power supply. The respective gate capacitances of NMOS transistor 602 and PMOS transistor 604 are controlled by the control signal D and the invert DB thereof. FIG. 6B is a graph illustrating the change of the capacitance of DCV 600 with a gate voltage applied at the gates of NMOS transistor 602 and PMOS transistor 604 under different control signals D and DB. The abscissa shows the gate voltage of NMOS transistor 602 and PMOS transistor 604, and the ordinate (“Params”) shows the capacitance of DCV 600. The bolded line labeled with Roman numeral I is a curve of the capacitance of DCV 600 when the control signal D is 1, and the non-bolded line labeled with Roman numeral II is a curve of the capacitance of DCV 600 when the control signal D is 0. As FIG. 6B shows, the capacitance of DCV 600 varies when the control signal D changes. Table I below lists the average, the range, and the linearity of the capacitance of DCV 600 under different control signals D and DB, where the linearity of the capacitance is calculated as the ratio of half of the range of capacitance to the average of the capacitance expressed in percentage.
TABLE IControlCapacitance (fF)ReferenceSignal DAverageRangeLinearityIGND1.041.06-1.03±1.5%IIVDD1.781.97-1.51±13%